1. Field of the Invention
The present invention relates to an equalizer circuit and a method of controlling the same. In particular, the present invention relates to an equalizer circuit, in which voltages of a first wiring and a second wiring which are connected to the equalizer circuit, and which causes the voltages to have offsets with respect to a midpoint voltage of the voltages supplied to the two wirings, and a method of controlling the same.
2. Description of the Related Art
A volatile semiconductor memory device (hereinafter, referred to as “memory”) such as a dynamic random access memory (DRAM) reads out data after differentially amplifying voltage difference generated in a pair of signal lines for the purpose of attaining high-speed operation. In the differential amplification, before reading out data, precharge operation and equalizing operation are performed for setting the voltages of the signal line pair to be substantially the same voltage (for example, a midpoint voltage between a power supply voltage and a ground voltage). After those operations are completed and an equalizer circuit is turned off, a gate transistor of a memory cell is made conductive, which generates a voltage difference between the signal lines of the pair. By differentially amplifying the voltage difference with a sense amplifier, the data is read out.
Further, in a DRAM, because charge held by a capacitor of the memory cell decreases over time and there is a fear that the stored data may be lost, it is necessary to perform a refresh operation to recharge the memory cell. Also in the refresh operation, first, the precharge operation is performed with respect to the signal line pair. Then, the gate transistor of the memory cell is made conductive and the voltage of one of the signal line pair is made close to the voltage of the memory cell, which generates a voltage, difference between the signal line pair. The voltage difference is differentially amplified by the sense amplifier to thereby increase the voltage of the signal line to which the memory cell is connected. As a result, the memory cell is recharged.
In recent years, many DRAMs are used also in portable equipment and the like. Therefore, those DRAMs are required to consume low power. However, a DRAM requires the refresh operation even when the DRAM is not accessed, and power is to be consumed in the refresh operation. Therefore, it is effective in lowering the power consumption of the DRAM to lower the power consumption in the refresh operation.
JP 2003-173679 A discloses a conventional technique relating to lowering of the power consumption in the refresh operation. The conventional technique decreases charge and discharge current with respect to a signal line pair by charge recycling. Further, by improving charge holding characteristics of the charge held in a capacitor of a memory cell, the frequency of the refresh operation is decreased. A semiconductor memory device according to the conventional technique lowers power consumption by those improvements.
An exemplary circuit disclosed in the conventional art is illustrated in FIG. 9. The circuit illustrated in FIG. 9 has sense amplifiers SA0 to SAn. A high-voltage-side power supply wiring SAP and a low-voltage-side power supply wiring SAN are each connected to the sense amplifiers SA0 to SAn. Further, one bit line Bit to which a memory cell is connected and the other bit line Bit_B for supplying a reference voltage to the sense amplifiers are each connected to the sense amplifiers SA0 to SAn. Still further, the bit lines Bit and Bit_B are connected to each other by an equalizer circuit EQ. The voltages of the bit lines Bit and Bit_B are the same when the equalizer circuit EQ is conductive. On the other hand, when the equalizer circuit EQ is nonconductive and the sense amplifiers SA0 to SAn are operated, the voltages of the bit lines Bit and Bit_B depend on an amount of charge stored in the memory cell, the voltage of the high-voltage-side power supply wiring SAP, and the voltage of the low-voltage-side power supply wiring SAN.
An NMOS transistor Ns is connected between the low-voltage-side power supply wiring SAN and a ground voltage VSS. A PMOS transistor Pd is connected between the high-voltage-side power supply wiring SAP and a power supply voltage VDD. Further, a PMOS transistor Pi is connected to the high-voltage-side power supply wiring SAP. A recycling capacitor CAP is connected between the PMOS transistor Pi and the ground voltage VSS.
FIG. 10 is a timing chart of the refresh operation of the circuit illustrated in FIG. 9. First, at a time Ta, the equalizer circuit is made nonconductive, the NMOS transistor Ns is made conductive, and the voltage of the low-voltage-side power supply wiring SAN is set as the ground voltage VSS. Further, the PMOS transistor Pi is made conductive, and the voltage of the high-voltage-side power supply wiring SAP set as VIID (i.e., voltage of a terminal of the recycling capacitor CAP on the side of the transistor Pi) (time Ta). In this case, the high-voltage-side power supply wiring SAP is charged with charge stored in the recycling capacitor CAP (time Tb), which operates the sense amplifiers SA0 to San. Accordingly, the voltages of the bit lines Bit and Bit_B are set based on the voltages of the high-voltage-side power supply wiring SAP and the low-voltage-side power supply wiring SAN, respectively.
Then, the PMOS transistor Pi is made nonconductive while the PMOS transistor Pd is made conductive. As a result, the voltage of the high-voltage-side power supply wiring SAP is set as the power supply voltage VDD. After that, the PMOS transistor Pi is made conductive while the PMOS transistor Pd is made nonconductive. As a result, the charge in the high-voltage-side power supply wiring SAP is stored (or recycled) in the recycling capacitor CAP, and the voltage of the high-voltage-side power supply wiring SAP is set as VIID (time Tc). Then, the PMOS transistor Pi and the NMOS transistor Ns are made nonconductive and the equalizer circuit EQ is made conductive to thereby connect the bit lines Bit and Bit_B to each other. As a result, the voltages of the bit lines Bit and Bit_B are set as the same voltage VIID/2 (time Td).
Specifically, in the conventional circuit, charge corresponding to the voltage difference between a first voltage (for example, the power supply voltage) and a second voltage (the voltage VIID) is stored in the recycling capacitor CAP. By recycling the stored charge in the subsequent refresh operation, consumption of the charge corresponding to the voltage difference is lowered to realize low power consumption.
Further, in the conventional circuit, the voltage of the bit lines Bit and Bit_B after the refresh operation (precharge voltage) is lower than half of the power supply voltage VDD. The precharge voltage is a reference voltage of the sense amplifiers. If the voltage becomes lower, time required for the voltage of the memory cell to drop due to leakage current to reach the reference voltage can be made longer. Specifically, the conventional circuit can decrease the frequency of the refresh operation. Further, the conventional circuit can lower the power consumption in the refresh operation.
However, the conventional circuit needs time for charging from the recycling capacitor CAP to the high-voltage-side power supply wiring SAP. There is a problem in that the charging time prevents a high-speed operation. Further, a capacitor generally requires a larger layout area than other elements. Therefore, when such a recycling capacitor is formed on the same substrate, there is a problem in that a chip area is increased.